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cys25g0101dx sonet oc-48 transceiver cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-02009 rev. *k revised july 27, 2007 features n sonet oc-48 operation n bellcore and itu jitter compliance n 2.488 gbaud serial signaling rate n multiple selectable loopback or loop through modes n single 155.52 mhz reference clock n transmit fifo for flexible data interface clocking n 16-bit parallel-to-serial conversion in transmit pa th n serial-to-16-bit parallel conversion in receive pat h n synchronous parallel interface p lvpecl compliant p hstl compliant n internal transmit and receive phase-locked loops (p lls) n differential cml serial input p 50 mv input sensitivity p 100 internal termination and dc restoration n differential cml serial output p source matched for 50 transmission lines (100 differential transmission lines) n direct interface to standard fiber optic modules n less than 1.0w typical power n 120-pin 14 mm 14 mm tqfp n standby power saving mode for inactive loops n 0.25 bicmos technology n pb-free packages available functional description the cys25g0101dx sonet oc-48 transceiver is a commu - nications building block for high speed sonet data communica- tions. it provides complete parallel-to-serial and serial-to-parallel conversion, clock generation, and clock and data re covery operations in a single chip optimized for full sone t compliance. transmit path new data is accepted at the 16-bit parallel transmi t interface at a rate of 155.52 mhz. this data is passed to a smal l integrated fifo to allow flexible transfer of data between the sonet processor and the transmit serializer. as each 16-b it word is read from the transmit fifo, it is serialized and sent o ut to the high speed differential line driver at a rate of 2.488 g bits/second. receive path as serial data is received at the differential line receiver, it is passed to a clock and data recovery (cdr) pll that extracts a precision low jitter clock from the transitions in the data stream. this bit rate clock is used to sample the data stre am and receive the data. every 16-bit times, a new word is present ed at the receive parallel interface along with a clock. parallel interface the parallel i/o interface supports high speed bus communica- tions using hstl signaling levels to minimize both power consumption and board landscape. the hstl outputs a re capable of driving unterminated transmission lines of less than 70 mm and terminated 50 transmission lines of more than twice that length. the cys25g0101dx transceiver?s parallel hstl i/o ca n also be configured to operate at lvpecl signaling levels . this is done externally by changing v ddq , v ref and creating a simple circuit at the termination of the transceiver?s par allel output interface.
cys25g0101dx document number: 38-02009 rev. *k page 2 of 17 16 txd[15:0] input register shifter txclki lockref tx pll x16 fifo in out 16 (155.52 mhz) looptime tx bit-clock refclk diagloop lineloop loopa 16 output register rxd[15:0] shifter rx cdr pll 16 rxclk (155.52 mhz) recovered bit-clock retimed data (155.52 mhz) lock-to-data/ clock control logic lock-to-ref lfi sd fifo_err txclko fifo_rst reset pwrdn logic block diagram
cys25g0101dx document number: 38-02009 rev. *k page 3 of 17 clocking the source clock for the transmit data path is sele ctable from either the recovered clock or an extern al bits (building integrated timing source) reference clock. the low jitter of t he cdr pll allows loop timed operation of the trans mit data path meeting all bellcore and itu jitter requirements. multiple loopback and loop through modes are availa ble for both diagnostic and normal operation. for s ystems containing redundant sonet rings that are maintained in standby, the cys 25g0101dx may also be dynamically powered down to c onserve system power. sonet data serial data optical xcvr rd+ rd? sd td? td+ in+ in? sd out? out+ serial data cys25g0101dx bits time reference 155.52 mhz refclk txd[15:0] txclki fifo_err txclko rxd[15:0] rxclk 2 looptime diagloop loopa lineloop reset pwrdn lockref lfi 16 16 processor transmit data interface receive data interface data & clock direction control status and system control host bus interface system or telco bus optical fiber links fifo_rst figure 1. cys25g0101dx system connections
cys25g0101dx document number: 38-02009 rev. *k page 4 of 17 pin configuration the pin configuration for 120-pin thin quad flatpac k follows. [1, 2] 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 27 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 5 6 57 58 59 60 61 62 65 64 63 70 69 68 67 66 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 lfi reset diag loop lineloo p loop a vssn vccn vssn sd lockref r xd[0] r xd[1] r xd[2] r xd[3] r xd[4] r xd[5] vssn vddq r xd[6] r xd[7] vssn vddq rxclk vssn vddq nc nc nc nc vssq n c n c vssn vd dq rxd[8] rxd[9] rxd[10] rxd[11] rxd[12] rxd[13] rxd [14] rxd[15] vssn vddq vcc n vssn fifo_err fifo_rst txd[15] txd[14] txd[13] txd[12] txclki vssn vcc n vref txd[11] txd[10] txd[9] txd[8] txd[7] txd[6] txd[5] txd[4] vssq vccq vssn vccn txd[3] txd[2] txd[1] txd[0] vssn vddq txclko vs sn vccn pw rdn lo optime nc refclk? refclk+ vs sq vccq nc nc nc vccq vssq nc vssq vssq vccq vccq o ut+ o ut? vccq cm_ser vssq in? in+ vssq vccq vccq \nc * vssq \nc * vssq \nc * nc rxcp2 rxcn2 rxcp1 rxcn1 cys25g0101dx top view v ssn vssn nc nc nc vssq vccq vc cq vccq 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 27 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 5 6 57 58 59 60 61 62 65 64 63 70 69 68 67 66 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 120 119 118 117 116 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 27 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 5 6 57 58 59 60 61 62 65 64 63 70 69 68 67 66 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 lfi reset diag loop lineloo p loop a vssn vccn vssn sd lockref r xd[0] r xd[1] r xd[2] r xd[3] r xd[4] r xd[5] vssn vddq r xd[6] r xd[7] vssn vddq rxclk vssn vddq nc nc nc nc vssq n c n c vssn vd dq rxd[8] rxd[9] rxd[10] rxd[11] rxd[12] rxd[13] rxd [14] rxd[15] vssn vddq vcc n vssn fifo_err fifo_rst 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 lfi reset diag loop lineloo p loop a vssn vccn vssn sd lockref r xd[0] r xd[1] r xd[2] r xd[3] r xd[4] r xd[5] vssn vddq r xd[6] r xd[7] vssn vddq rxclk vssn vddq nc nc nc nc vssq n c n c vssn vd dq rxd[8] rxd[9] rxd[10] rxd[11] rxd[12] rxd[13] rxd [14] rxd[15] vssn vddq vcc n vssn fifo_err fifo_rst txd[15] txd[14] txd[13] txd[12] txclki vssn vcc n vref txd[11] txd[10] txd[9] txd[8] txd[7] txd[6] txd[5] txd[4] vssq vccq vssn vccn txd[3] txd[2] txd[1] txd[0] vssn vddq txclko vs sn vccn pw rdn lo optime nc refclk? refclk+ vs sq vccq nc nc nc vccq vssq nc vssq vssq vccq vccq o ut+ o ut? vccq cm_ser vssq in? in+ vssq vccq vccq \nc * vssq \nc * vssq \nc * nc rxcp2 rxcn2 rxcp1 rxcn1 cys25g0101dx top view v ssn vssn nc nc nc vssq vccq vc cq vccq figure 2. 120-pin thin quad flatpack pin configura tion notes 1. no connect (nc) pins are left unconnected or floa ting. connecting any of these pins to the positive or negative power supply causes improper operation or failure of the device. 2. pins 113 and 119 are either no connect or vssq. u se vssq for compatibility with next generation of o c-48 serdes devices. pin 116 are either no connect or vccq. use vccq for compatibility with next generation of oc-48 serdes devices.
cys25g0101dx document number: 38-02009 rev. *k page 5 of 17 pin descriptions cys25g0101dx oc-48 sonet transceiver pin name i/o characteristics signal description transmit path signals txd[15:0] hstl inputs, sampled by txclki parallel transmit data inputs . a 16-bit word, sampled by txclki . txd[15] is the most significant bit (the first bit transmitted). txclki hstl clock input parallel transmit data input clock . the txclki is used to transfer the data into the input register of the serializer. the txclki samples the data, txd [15:0], on the rising edge of the clock cycle. txclko hstl clock output transmit clock output . divide by 16 of the selected transmit bit rate cl ock. it is used to coordinate byte wide transfers between upstream log ic and the cys25g0101dx. v ref input analog reference reference voltage for hstl parallel input bus . v ddq /2. [3] receive path signals rxd[15:0] hstl output, synchronous parallel receive data output . these outputs change following rxclk . rxd[15] is the most significant bit of the output word and is rece ived first on the serial interface. rxclk hstl clock output receive clock output . divide by 16 of the bit rate clock extracted from the received serial stream. rxd [15:0] is clocked out on the falling ed ge of the rxclk. cm_ser analog common mode termination . capacitor shunt to v ss for common mode noise. rxcn1 analog receive loop filter capacitor (negative) . rxcn2 analog receive loop filter capacitor (negative) . rxcp1 analog receive loop filter capacitor (positive) . rxcp 2 analog receive loop filter capacitor (positive). device control and status signals refclk differential lvpecl input reference clock . this clock input is used as the timing reference for the transmit and receive plls. a derivative of this input clock is u sed to clock the transmit parallel interface. the reference clock is internally biased enabling f or an ac coupled clock signal. lfi lvttl output line fault indicator . when low, this signal indicates that the selected receive data stream is detected as invalid by either a low input on sd or by the receive vco operated outside its specified limits. reset lvttl input reset for all logic functions except the transmit fifo. lockref lvttl input receive pll lock to reference . when low, the receive pll locks to refclk instead of the received serial data stream. sd lvttl input signal detect . when low, the receive pll locks to refclk instead of the received serial data stream. the sd needs to be connected to an ext ernal optical module to indicate a loss of received optical power. fifo_err lvttl output transmit fifo error . when high, the transmit fifo has either under or overflowed. when this occurs, the fifo?s internal clearing mech anism clears the fifo within nine clock cycles. in addition, fifo_rst is activated at device power up to ensure that the in and out pointers of the fifo are set to maximum separation. fifo_rst lvttl input transmit fifo reset . when low, the in and out pointers of the transmit fifo are set to maximum separation. fifo_rst is activated at device power up to ensure that the in and out pointers of the fifo are set to maximum separat ion. when the fifo is reset, the output data is a 1010... pattern. pwrdn lvttl input device power down . when low, the logic and drivers are all disabled and placed into a standby condition where only minimal power is dissi pated. note 3. v ref equals to (v cc ? 1.33v) if interfacing to a parallel lvpecl inter face.
cys25g0101dx document number: 38-02009 rev. *k page 6 of 17 cys25g0101dx operation the cys25g0101dx is a highly configurable device de signed to support reliable transfer of large quantities of data using high speed serial links. it performs necessary clock and data recovery, clock generation, serial-to-parallel conv ersion, and parallel-to-serial conversion. cys25g0101dx also pr ovides various loopback functions. cys25g0101dx transmit data path operating modes the transmit path of the cys25g0101dx supports 16-b it wide data paths. phase align buffer data from the input register is passed to a phase a lign buffer (fifo). this buffer is used to absorb clock phase d ifferences between the transmit input clock and the internal c haracter clock. initialization of the phase align buffer takes plac e when the fifo_rst input is asserted low. when fifo_rst is returned high, the present input clock phase, relative to tx clko, is set. once set, the input clock is allowed to skew in tim e up to half a character period in either direction relative to re fclk (that is, 180 ) . this time shift allows the delay path of the char acter clock (relative to reflck) to change due to operating vol tage and temperature not affecting the desired operation. fi fo_rst is an asynchronous input. fifo_err is the transmit fifo e rror indicator. when high, the transmit fifo has either under or overflowed. the fifo is externally reset to clear t he error indication; or if no action is taken, the internal clearing mechanism clears the fifo in nine clock cycles. whe n the fifo is being reset, the output data is 1010. transmit pll clock multiplier the transmit pll clock multiplier accepts a 155.52 mhz external clock at the refclk input. it multiplies t hat clock by 16 to generate a bit rate clock for use by the transmi t shifter. the operating serial signaling rate and allowable range of refclk frequencies is listed in table 7 on page 11. the refclk phase noise limits to meet sonet compliancy are shown in figure 6 on page 13. the refclk input is a standard lvpecl input. loop control signals diagloop lvttl input diagnostic loopback control . when high, transmit data is routed through the re ceive clock and data recovery. it is then presented at th e rxd[15:0] outputs. when low, received serial data is routed through the receive clock and data recovery. it is then presented at the rxd[15:0] outputs. lineloop lvttl input line loopback control . when high, received serial data is looped back fr om receive to transmit after being reclocked by a recovered clock . when lineloop is low, the data passed to the out line driver is controlled by loo pa. when both lineloop and loopa are low, the data passed to the out line driver is generated in the transmit shifter. loopa lvttl input analog line loopback . when lineloop is low and loopa is high, received serial data is looped back from receive input buffer to tr ansmit output buffer but is not routed through the clock and data recovery pll. when loopa is low, the data passed to the out line driver is controlled by lineloop. looptime lvttl input loop time mode . when high, the extracted receive bit clock replac es transmit bit clock. when low, the refclk input is multiplied by 16 to g enerate the transmit bit clock. serial i/o out differential cml output differential serial data output . this differential cml output (+3.3v referenced) i s capable of driving terminated 50 transmission lines or commercial fiber optic trans mitter modules. in differential cml input differential serial data input . this differential input accepts the serial data s tream for deserialization and clock extraction. power v ccn power +3.3v supply (for digital and low speed io fun ctions) v ssn ground signal and power ground (for digital and low speed io functions) v ccq power +3.3v quiet power (for analog functions) v ssq ground quiet ground (for analog functions) v ddq power +1.5v supply for hstl outputs [4] cys25g0101dx oc-48 sonet transceiver (continued) pin name i/o characteristics signal description note 4. v ddq equals v cc if interfacing to a parallel lvpecl interface.
cys25g0101dx document number: 38-02009 rev. *k page 7 of 17 serializer the parallel data from the phase align buffer is pa ssed to the serializer that converts the parallel data to seria l data. it uses the bit rate clock generated by the transmit pll clock multiplier. txd[15] is the most significant bit of the output w ord and is trans- mitted first on the serial interface. serial output driver the serial interface output driver makes use of hig h perfor- mance differential current mode logic (cml) to prov ide a source matched driver for the transmission lines. this dri ver receives its data from the transmit shifters or the receive loop back data. the outputs have signal swings equivalent to that of st andard lvpecl drivers and are capable of driving ac couple d optical modules or transmission lines. cys25g0101dx receive data path serial line receivers a differential line receiver, in, is available for accepting the input serial data stream. the serial line receiver inputs accommodate high wire interconnect and filtering losses or tran smission line attenuation (v se > 25 mv, or 50 mv peak-to-peak differential). it can be ac coupled to +3.3v or +5v powered fiber opt ic interface modules. the common mode tolerance of these line re ceivers accommodates a wide range of signal termination vol tages. lock to data control line receiver routed to the clock and data recovery pll is monitored for: n status of signal detect (sd) pin n status of lockref pin. this status is presented on the line fault indicato r (lfi ) output, that changes asynchronously in the cases in which s d or lockref go from high to low. otherwise, it changes synchronously to the refclk. clock data recovery the extraction of a bit rate clock and recovery of data bits from received serial stream is performed by a clock data recovery (cdr) block. the clock extraction function is perfo rmed by high performance embedded phase-locked loop (pll) that t racks the frequency of the incoming bit stream and aligns the phase of the internal bit rate clock to the transitions in the s elected serial data stream. cdr accepts a character rate (bit rate * 16) refere nce clock on the refclk input. this refclk input is used to ensu re that the vco (within the cdr) is operating at the correct fr equency (rather than some harmonic of the bit rate), to imp rove pll acquisition time and to limit unlocked frequency ex cursions of the cdr vco when no data is present at the serial input s. regardless of the type of signal present, the cdr a ttempts to recover a data stream from it. if the frequency of the recovered data stream is outside the limits set by the range controls, the cdr pll tracks refclk instead of the data stream. w hen the frequency of the selected data stream returns to a valid frequency, the cdr pll is allowed to track the rece ived data stream. the frequency of refclk must be within 100 ppm of the frequency of the clock that drives the refclk s ignal of the remote transmitter to ensure a lock to the incoming data stream. for systems using multiple or redundant connections , the lfi output can be used to select an alternate data stre am. when an lfi indication is detected, external logic toggles sel ection of the input device. when such a port switch takes place, it is necessary for the pll to reacquire lock to the new serial stream. external filter the cdr circuit uses external capacitors for the pl l filter. a 0.1 f capacitor needs to be connected between rxcn1 and rxcp1. similarly a 0.1 f capacitor needs to be connected between rxcn2 and rxcp2. the recommended packages a nd dielectric material for these capacitors are 0805 x 7r or 0603 x7r. deserializer the cdr circuit extracts bits from the serial data stream and clocks these bits into the deserializer at the bit clock rate. the deserializer converts serial data into parallel dat a. rxd[15] is the most significant bit of the output word and is rece ived first on the serial interface. loopback timing modes cys25g0101dx supports various loopback modes, as described in the following sections. facility loopback (line loopback with retiming) when the lineloop signal is set high, the facility loopback mode is activated and the high speed serial receive data (in) is presented to the high speed transmit output (out) after retiming. in facility loopback mode, the high speed receive data (in) is also converted to parallel data and presen ted to the low speed receive data output pins (rxd[15:0]). the rec eive recovered clock is also divided down and presented to the low-speed clock output (rxclk). equipment loopback (diagnostic loopback with retimi ng) when the diagloop signal is set high, transmit data is looped back to the rx pll, replacing in. data is looped b ack from the parallel tx inputs to the parallel rx outputs. the data is looped back at the internal serial interface and goes thro ugh transmit shifter and the receive cdr. sd is ignored in this mode. line loopback mode (non-retimed data) when the loopa signal is set high, the rx serial da ta is directly buffered out to the transmit serial data. the data at the serial output is not retimed. loop timing mode when the looptime signal is set high, the tx pll is bypassed and the receive bit rate clock is used for the transmit side shifter. reset modes all logic circuits in the device are reset using re set and fifo_rst signals. when reset is set low, all logic circuits except fifo are internally reset. when fifo_rst is set low, the fifo logic is reset.
cys25g0101dx document number: 38-02009 rev. *k page 8 of 17 power down mode cys25g0101dx provides a global power down signal pw rdn . when low, this signal powers down the entire device to a minimal power dissipation state. reset and fifo_rst signals should be asserted low along with pwrdn signal to ensure low power dissipation. lvpecl compliance the cys25g0101dx hstl parallel i/o can be configure d to lvpecl compliance with slight termination modificat ions. on the transmit side of the transceiver, the txd[15:0] and txclki are made lvpecl compliant by setting v ref (reference voltage of a lvpecl signal) to v cc ? 1.33v. to emulate an lvpecl signal on the receiver side, set the vddq to 3.3v a nd the trans- mission lines needs to be terminated with the thve nin equiv- alent of z at lvpecl ref. the signal is then attenuated using a series resistor at the driver end of the line to re duce the 3.3v swing level to an lvpecl swing level (see figure 10 ). this circuit needs to be used on all 16 rxd[15:0] pins, txclko, and rxclk. the voltage divider is calculated assuming t he system is built with 50 transmission lines. maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. storage temperature ............................... .. ?65c to +150c ambient temperature with power applied ...................................... ...... ?55c to +125c v cc supply voltage to ground potential ........?0.5v to +4.2v v ddq supply voltage to ground potential ......?0.5v to + 4.2v dc voltage applied to hstl outputs in high z state .................................... . ?0.5v to v ddq + 0.5v dc voltage applied to other outputs in high z state .................................... ... ?0.5v to v cc + 0.5v output current into lvttl outputs (low) ............ ..... 30 ma dc input voltage ................................... ?0.5v to v cc + 0.5v static discharge voltage........................... ................ > 1100v (mil-std-883, method 3015) latch up current................................... .................. > 200 ma power up requirements power supply sequencing is not required if you are configuring v ddq =3.3v and all power supplies pins are connected to the same 3.3v power supply. power supply sequencing is required if you are conf iguring v ddq =1.5v. power is applied in the following sequence: v cc (3.3) followed by v ddq (1.5). power supply ramping may occur simultaneously as long as the v cc /v ddq relationship is maintained. operating range range ambient temperature v ddq v cc commercial 0c to +70c 1.4v to 1.6v [4] 3.3v 10% industrial ?40c to +85c 1.4v to 1.6v [4] 3.3v 10% table 1. dc specifications?lvttl parameter description test conditions min max unit lvttl outputs v oht output high voltage v cc = min, i oh = ?10.0 ma 2.4 v v olt output low voltage v cc = min, i ol = 10.0 ma 0.4 v i os output short circuit current v out = 0v ?20 ?90 ma lvttl inputs v iht input high voltage low = 2.1v, high = v cc + 0.5v 2.1 v cc ? 0.3 v v ilt input low voltage low = ?3.0v, high = 0.8 ?0.3 0.8 v i iht input high current v cc = max, v in = v cc 50 a i ilt input low current v cc = max, v in = 0v ?50 a capacitance c in input capacitance v cc = max, at f = 1 mhz 5 pf
cys25g0101dx document number: 38-02009 rev. *k page 9 of 17 table 2. dc specifications?power parameter description test conditions typ max unit power i cc1 active power supply current 300 347 ma i sb standby current 5 ma table 3. dc specifications?differential lvpecl com patible inputs (refclk) the dc specifications?differential lvpecl compatibl e inputs (refclk) follow. [5] parameter description test conditions min max unit v insgle input single-ended swing 200 600 mv v diffe input differential voltage 400 1200 mv v iehh highest input high voltage v cc ? 1.2 v cc ? 0.3 v v iell lowest input low voltage v cc ? 2.0 v cc ? 1.45 v i ieh input high current v in = v iehh max. 750 a i iel input low current v in = v iell min. ?200 a capacitance c ine input capacitance 4 pf table 4. dc specifications?differential cml the dc specifications?differential cml follow. [5] parameter description test conditions min max unit transmitter cml compatible outputs v ohc output high voltage (v cc referenced) 100 differential load v cc ? 0.5 v cc ? 0.15 v v olc output low voltage (v cc referenced) 100 differential load v cc ? 1.2 v cc ? 0.7 v v diffoc output differential swing 100 differential load 560 1600 mv v sglco output single-ended voltage 100 differential load 280 800 mv receiver cml compatible inputs v insglc input single-ended swing 25 1000 mv v diffc input differential voltage 50 2000 mv v ichh highest input high voltage v cc v v icll lowest input low voltage 1.2 v v (+ ) v (-) v d 0 .0 v v d if f = v (+ )-v (-) v s g l figure 3. differential waveform definition 5. see figure 3 for differential waveform definition.
cys25g0101dx document number: 38-02009 rev. *k page 10 of 17 ac waveforms ac test loads table 5. dc specifications?hstl parameter description test conditions min max unit hstl outputs v ohh output high voltage v cc = min, i oh = ?4.0 ma v ddq ? 0.4 v v olh output low voltage v cc = min, i ol = 4.0 ma 0.4 v i osh output short circuit current v out = 0v 100 ma hstl inputs v ihh input high voltage v ref + 0.13 v ddq + 0.3 v v ilh input low voltage ?0.3 v ref ? 0.1 v i ihh input high current v ddq = max, v in = v ddq 50 a i ilh input low current v ddq = max, v in = 0v ?40 a capacitance c inh input capacitance v ddq = max, at f = 1 mhz 5 pf 2.0v 0.8v 3.0v gnd 2.0v 0.8v < 1 ns < 1 ns 80% 20% 80% 20% v ichh 3.0v v icll v th = 1.4v v th = 1.4v < 150 ps < 150 ps 80% 20% 80% 20% v iehh v iell < 1.0 ns < 1.0 ns (a) lvttl input test waveform (b) cml input test waveform (d) lvpecl input test waveform < 1 ns < 1 ns (c) hstl input test waveform v th = 0.75v v th = 0.75v v ihh v ihl 80% 20% 80% 20% 3.3v output (a) ttl ac test load (b) cml ac test load r1 r2 c l r l r1 = 330 r2 = 510 (includes fixture and probe capacitance) r l = 100 c l 10 p f 1.5v output (c) hstl ac test load r1 r2 c l r1 = 100 r2 = 100 (includes fixture and probe capacitance) c l 7 pf out+ out?
cys25g0101dx document number: 38-02009 rev. *k page 11 of 17 ac specifications table 6. ac specifications?parallel interface parameter description min max unit t ts txclki frequency (must be frequency coherent to ref clk) 154.5 156.5 mhz t txclki txclki period 6.38 6.47 ns t txclkid txclki duty cycle 40 60 % t txclkir txclki rise time 0.3 1.5 ns t txclkif txclki fall time 0.3 1.5 ns t txds write data setup to of txclki 1.5 ns t txdh write data hold from of txclki 0.5 ns t tos txclko frequency 154.5 156.5 mhz t txclko txclko period 6.38 6.47 ns t txclkod txclko duty cycle 43 57 % t txclkor txclko rise time 0.3 1.5 ns t txclkof txclko fall time 0.3 1.5 ns t rs rxclk frequency 154.5 156.5 mhz t rxclk rxclk period 6.38 6.47 ns t rxclkd rxclk duty cycle 43 57 % t rxclkr rxclk rise time [6] 0.3 1.5 ns t rxclkf rxclk fall time [6] 0.3 1.5 ns t rxds recovered data setup with reference to of rxclk 2.2 ns t rxdh recovered data hold with reference to of rxclk 2.2 ns t rxpd valid propagation delay ?1.0 1.0 ns table 7. ac specifications?refclk the ac specifications?refclk follow. [7] parameter description min max unit t ref refclk input frequency 154.5 156.5 mhz t refp refclk period 6.38 6.47 ns t refd refclk duty cycle 35 65 % t reft refclk frequency tolerance ? (relative to received serial data) [8] ?100 +100 ppm t refr refclk rise time 0.3 1.5 ns t reff refclk fall time 0.3 1.5 ns table 8. ac specifications?cml serial outputs parameter description min typical max unit t rise cml output rise time (20?80%, 100 balanced load) 60 170 ps t fall cml output fall time (80?20%, 100 balanced load) 60 170 ps notes 6. rxclk rise time and fall times are measured at th e 20 to 80 percentile region of the rising and fall ing edge of the clock signal. 7. the 155.52 mhz reference clock phase noise limits for the cys25g0101dx are shown in figure 6 . 8. + 20 ppm is required to meet the sonet output frequen cy specification.
cys25g0101dx document number: 38-02009 rev. *k page 12 of 17 jitter waveforms the jitter transfer waveform of cys25g0101dx follow s. [12] . table 9. jitter specifications parameter description min typical [10] max [10] unit t tj-txpll total output jitter for tx pll (p-p) [9] 0.03 0.04 ui total output jitter for tx pll (rms) [9, 11] 0.007 0.008 ui t tj-rxpll total output jitter for rx cdr pll (p-p) [9] 0.035 0.05 ui total output jitter for rx cdr pll (rms) [9, 11] 0.008 0.01 ui notes 9. the rms and p-to-p jitter values are measured usi ng a 12 khz to 20 mhz sonet filter. 10. typical values are measured at room temperature and the max values are measured at 0 c. 11. this device passes the bellcore specification fr om -10 c to 85 c. 12. the bench jitter measurements are performed usin g an agilent omni bert sonet jitter tester. figure 4. jitter transfer waveform of cys25g0101dx the jitter tolerance waveform of cys25g0101dx follo ws. [12] figure 5. jitter tolerance waveform of cys25g0101d x
cys25g0101dx document number: 38-02009 rev. *k page 13 of 17 figure 6. cys25g0101dx reference clock phase noise limits switching waveforms transmit interface timing receive interface timing cys25g0101dx reference clock phase noise limits -155 -145 -135 -125 -115 -105 -95 -85 -75 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 frequency (hz) phase noise (dbc) txclko t txclkodl t txclkodh t txclko txclko t txclkodl t txclkodl t txclkodh t txclkodh t txclko t txclko txclki txd[15:0] t txds t txdh t txclkidl t txclkidh t txclki txclki txd[15:0] t txds t txds t txdh t txdh t txclkidl t txclkidl t txclkidh t txclkidh t txclki t txclki
cys25g0101dx document number: 38-02009 rev. *k page 14 of 17 typical io terminations figure 7. serial input termination figure 8. serial output termination [13] figure 9. txclko/ rxclk termination figure 10. rxd[15:0] termination figure 11. lvpecl compliant output termination out+ out? limiting amp in+ in? 100 0.1 f 0.1 f cy s25g0101dx zo=50 zo=50 out+ out? cy s25g0101dx in+ in? 100 0.1 f 0.1 f optical module zo=50 zo=50 hstl outpu t cy s25g0101dx 100 framer zo=50 hstl input 100 vddq=1.5v hstl outpu t cy s25g0101dx framer zo=50 hstl input rxd[15;0], rxclk, txclko cy s25g0101dx 121 framer zo=50 80.6 vddq=3.3v output vddq=3.3v 137 lvpecl input note 13. serial output of cys25g0101dx is source matched to 50 transmission lines (100 differential transmission lines).
cys25g0101dx document number: 38-02009 rev. *k page 15 of 17 figure 12. ac coupled clock oscillator termination figure 13. clock oscillator termination lvpec l output clock oscillator cy s25g0101dx zo=50 refcloc k i nter nall y biased 82 vcc 130 zo=50 82 vcc 130 0.1uf 0.1uf vcc lvpec l output clock oscillator cy s25g0101dx zo=50 reference cloc k input 82 vcc 130 zo=50 82 vcc 130
cys25g0101dx document number: 38-02009 rev. *k page 16 of 17 ordering information speed ordering code package name package type operating range standard cys25g0101dx-atc at120 120-pin tqfp commercial standard cys25g0101dx-atxc at120 120-pin pb-free tqfp commercial standard cys25g0101dx-ati at120 120-pin tqfp industrial standard CYS25G0101DX-ATXI at120 120-pin pb-free tqfp industrial package diagram figure 14. 120-pin thin quad flatpack (14 14 1 .4 mm) with heat slug at120 51-85116-**
document number: 38-02009 rev. *k revised july 27, 2 007 page 17 of 17 psoc designer?, programmable system-on-chip?, and psoc express? are trademarks and psoc? is a registered tr ademark of cypress semiconductor corp. all other trade marks or registered trademarks referenced herein are property of the res pective corporations. purchase of i 2 c components from cypress or one of its sublicensed as sociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. all products and company names mentioned in this document may be the trademarks of th eir respective holders. cys25g0101dx ? cypress semiconductor corporation, 2001 - 2007. the information contained herein is subject to change withou t notice. cypress semiconductor corporation assumes n o responsibility for the use of any circuitry other than circuitry embodied in a cypr ess product. nor does it convey or imply any license un der patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or s afety applications, unless pursuant to an express writte n agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expected to resu lt in significant injury to the user. the inclusion of cypre ss products in life-support systems application implies that the manufacturer assume s all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subject to worldwide patent protecti on (united states and foreign), united states copyright laws and international treaty pro visions. cypress hereby grants to licensee a personal, n on-exclusive, non-transferable license to copy, use, m odify, create derivative works of, and compile the cypress source code and derivative wor ks for the sole purpose of creating custom software a nd or firmware in support of licensee product to be use d only in conjunction with a cypress integrated circuit as specified in the applicable agreement . any reproduction, modification, translation, compilation, or representation of this source code except as speci fied above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, exp ress or implied, with regard to this material, incl uding, but not limited to, the implied warranties of merchantability and fitness for a particular pur pose. cypress reserves the right to make changes with out further notice to the materials described herein. cy press does not assume any liability arising out of the application or use o f any product or circuit described herein. cypress does not authorize its products for use as critical componen ts in life-support systems where a malfunction or failure may reasonably be expected to r esult in significant injury to the user. the inclusion of cyp ress? product in a life-support systems application implie s that the manufacturer assumes all risk of such use and in doing so indemnifies cy press against all charges. use may be limited by and subject to the applicable cypre ss software license agreement. document history document title: cys25g0101dx sonet oc-48 transceive r document number: 38-02009 rev. ecn no. issue date orig. of change description of change ** 105847 03/22/01 szv change from specification number : 38-00894 to 38-02009. *a 108024 06/20/01 amv changed marketing part number. *b 111834 12/18/01 cgx updated power specification in f eatures and dc specifications section. changed pinout for compatibility with cys25g0102dx in pin diagram and descriptions. verbiage added or changed for clarity in pin descriptions section. changed input sensitivity in receive data path section, page 6. rxclk rise time corrected to 0.3 nsec min cml and l vpecl input waveforms updated in test load and waveform section . diagrams replaced for clarity figures 1-10. added two refclock diagra ms figures 9 and 10. *c 112712 02/06/02 tme updated temperature range, stati c discharge voltage, and max total rms jitter. *d 113791 04/24/02 cgx updated the single ended swing a nd differential swing voltage for receiver cml compatible inputs. created a separate table sho wing peak to peak and rms jitter for both tx pll and rx pll . *e 115940 05/22/02 tme added industrial temperature spe cification to pages 8, 11, and 15. *f 117906 09/06/02 cgx added differential waveform defi nition. added bga pinout and package information. changed lvttl v iht min from 2.0 to 2.1 volts. *g 119267 10/17/02 cgx added phase noise limits data. removed bga pinout and package information. removed references to cys25g0102dx. *h 121019 11/06/02 cgx removed ?preliminary? from datas heet *i 122319 12/30/02 rbi added power up requirements to m aximum ratings information *j 124438 02/13/03 wai revised power up requirements *k 1309983 07/27/07 ius/sfv added pb-free logo added pb-free parts to the ordering information: cys25g0101dx-atxc, CYS25G0101DX-ATXI

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